tout ca ne change rien au fonds du problème, à partir du moment ou la transmission est synchrone (ce qui est le cas du SPDIF) il faudra forcément un asservissement de l'horloge de sortie par l'horloge source.
J'ai fait quelques recherches dans le matériel "pro" qui sont en général mieux documentés techniquement et j'ai trouvé une marque qui commercialise des DAC avec buffer : Lavry Engineering.
Le DA-924 :
http://www.lavryengineering.com/da924.html
Dans la doc : http://www.lavryengineering.com/pdfs/DA924m.pdf
Page 4
The DA924 eliminates jitter in the incoming data stream by use of a DSP controlled pullable crystal oscillator and a short buffer memory for temporary storage of the incoming data. The DSP transfers the data from the memory to the DAC disregarding any jitter in the input frequency. A proprietary fast-lock high-accuracy measurement compares the average input frequency to the oscillator frequency and makes the appropriate adjustments. The adjustments are done with sub pico-second resolution, to insure minimum interference with signal reconstruction.
Page 7
CrystalLock™ and Wide lock
The DA924 eliminates jitter in the incoming data stream by use CrystalLock™, a DSP controlled pullable crystal oscillator and a short buffer memory for temporary storage of the incoming data. The DSP transfers the data from the memory to the DAC disregarding any jitter in the input frequency. A proprietary fast-lock high-accuracy measurement compares the average input frequency to the oscillator frequency and makes the appropriate adjustments. The adjustments are done with sub pico-second resolution, to insure minimum interference with signal reconstruction.
CrystalLock™ meets and exceeds the AES lock range requirements ( +/- 100ppm). Such narrow lock allows the use of pullable crystal oscillators, thus yielding the best performance from a jitter standpoint. The DA924 provides a wide lock mode for tracking sample rates between 40 and 50KHz, and 86 and 98kHz. Clock jitter levels increase when using varispeed, thus its use should be restricted for sample rates outside of the narrow lock range. Some multi-channel uses of the DA924 may require varispeed for synchronization.
Page 10 :
Jitter removal
Ordinary phase lock loops circuits (PLLs) do a reasonable job at removing high frequency jitter from the incoming clock. The same circuits perform very poorly in the removal of low frequency jitter from the clock signal. The need to keep enough bandwidth for locking to and tracking the incoming data translates to zero rejection of low frequency jitter content (typically hundreds of Hz of zero rejection bandwidth). While some of the jitter content is random, much is due to coupling of the data itself into the receiver circuitry.
The DA924 uses a non standard approach for removing jitter. The deglitcher circuit is clocked by a pullable crystal oscillator but the control signal for the crystal is freed from having to track down incoming clock variations. The clock oscillator is controlled by a processor driven DAC (not an ordinary phase detector plus filter circuit). The oscillator frequency is change by tiny amounts (.1ppm) and not very often (15 seconds or more) in a manner allowing it to track only very long term average drift. Using such an approach with ordinary PLL will cause loss of lock because the slight variations in incoming data rate cause loss of correspondence between the input and the too steady of a clock circuit. The DA924 CrystalLock (TM) approach, stores enough data in a dedicated memory to guarantee that each clock cycle can find its data. Moving the clock slowly to track the long term average drift is done just fast enough to make sure that the buffer memory does not overfill or becomes empty.At first glance one may get concerned about the potential long delay due to storage of a lot of data samples. In fact, the data storage is very small and so is the delay. An "unrealistic" 100ppm per second input rate step requires pre storage of about 5 words of data for 1 second D/A stepping, or an 50 word memory for 10 seconds of D/A update rate.
Y a bien un asservissement obligatoire sur l'horloge source, ca peut pas marcher autrement en fait
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Créé le 16 Jan 2020 12:19
